1. Field of the Invention
The present invention relates to a semiconductor device technique and, more particularly, to a semiconductor device having a conducting portion of upper and lower conductive layers and a method of fabricating the same.
2. Description of the Related Art
The conventional semiconductor device disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2003-298005 includes solder balls as connecting terminals for external connection outside the size of a silicon substrate. Therefore, this semiconductor device has a structure in which a silicon substrate having a plurality of connecting pads on its upper surface is formed on the upper surface of a base plate, an insulating layer is formed on the upper surface of the base plate around the silicon substrate, an upper insulating film is formed on the upper surfaces of the silicon substrate and insulating layer, upper interconnections are formed on the upper surface of the upper insulating film and electrically connected to the connecting pads of the silicon substrate, portions except for connecting pad portions of the upper interconnections are covered with an overcoat film, and solder balls are formed on the connecting pad portions of the upper interconnections.
In this conventional semiconductor device, the upper interconnections are formed only above the silicon substrate and on insulating layer. To effectively use the space, it is also possible to form interconnections on the upper or lower surface of the base plate, and connect a portion of the interconnections to a portion of the upper interconnections via a vertical conducting portion extended in a through hole formed in the insulating layer and base plate. In this structure, however, the insulating layer and base plate are present outside the vertical conducting portion in the through hole formed in the insulating layer and base plate. This unnecessarily increases the size of the semiconductor device.